As Dynamic Random Access Memories (DRAM) grow larger and are built with smaller geometries, undesirable parasitic capacitances between lengthy conductors are becoming more prevalent. A simple diagram of a portion of a DRAM integrated circuit is shown in FIGS. 1A and 1B. The disclosed DRAM includes several subarrays 16, each of which contains a portion of the memory array. Thus, for example, a 16M-bit memory array might be broken up into 64 256K-bit subarrays. As one of skill in the art of DRAM architecture will understand, the columns 14, or digit lines, in the subarrays 16 in FIGS. 1A and 1B run from up and down and the rows in the subarrays run left to right (not shown).
The digit lines 14 connect to sense amps 13 which reside between the subarrays 16, and the rows connect to row decodes 15 which also reside between the subarrays 16. As is commonplace in the industry, the digit lines 14 are arranged such that a particular sense amp 13 receives a complementary (opposite) pair of logic signals, represented in FIG. 1B as DIGIT and DIGIT*. For example, when DIGIT=logic `1` (typically 5 Volts or less), DIGIT*=logic `0` (typically 0 Volts), and vice versa. After sensing, and when a given digit line pair 14 is selected by the application of signal CS, the logic of digit lines DIGIT and DIGIT* are transferred to the I/O lines 17 that run through the sense amps 13. Like the digit lines 14, the I/O lines 17 are also complementary, as represented by I/O and I/O*. If these I/O lines 17 appear within a selected section, as denoted by the application of signal "SECTION," they are transferred, again in complementary form, to the data lines 18 which run along side the row decodes 15. ("Data lines" should be interpreted for purposes of this disclose as distinct from the "digit lines" that appear within the subarrays). Ultimately, the data line pairs 18 are input into a data line amplifier 19, which in turn sends a selected data line 18 (selection not shown) to the data path 20 which interfaces with the rest of the DRAM's peripheral circuitry. In a preferred embodiment, the data line pairs 18 constitute conductors that run along side the row decode 15 before making contact with the data line amplifier 19. These data line pairs 18 together constitute a data line bus 21.
It is known in the prior art that as the length of conductors increases and as the spacing between them decreases that the capacitive coupling between conductors increases, thus negatively affecting the speed at which signals can be conducted. Heretofore, this problem has been particularly acute with respect to the digit lines 14 in the array, which are typically very long, very thin, and spaced at minimum distances with respect to one another. Accordingly, the prior art has employed methods of "twisting" the digit lines 14 to try and reduce the effects of parasitic capacitance between digit lines.
As shown in FIG. 2A, which can be described as a non-twisted architecture for the digit lines 14, a "worst case" and "best case" scenario with respect to the parasitic capacitance 26 can be obtained. In the worst case, the effect of parasitic capacitance 26 is maximized. For example, suppose a `1` logic state appears on digit line Digit0. In this case, Digit0* will necessarily be held at a complementary `0` logic state. If Digit1* is also held at logic `0,` then Digit0 will be surrounded for its entire length by digit lines of the opposite data states. Because Digit0 is completely surrounded on both sides by the opposite logic state, the ability to transport a logic `1` is negatively affected to the greatest extent possible. The coupling coefficient of Digit0 for this worse case scenario can be defined as C=1.
In the best case, the effect of parasitic capacitance 26 is minimized. For example, suppose a `1` logic state appears on digit line Digit3*, and that adjacent digit line Digit2 is also held at `1.` Although the complementary digit line Digit3 is necessarily at the opposite logic state, the fact that there is no voltage difference between Digit3* and Digit2 works to effectively eradicate the parasitic capacitance 26 between these two digit lines. Hence, Digit3* can be accessed faster than Digit0 (i.e., the worst case) due to the reduction in parasitic capacitance. Because Digit3* is surrounded on only one side by the opposite logic state, the coupling coefficient of this best case scenario can be defined as C=0.5.
It is known in the prior art that the digit line pairs 14 can be twisted to reduce the effect of intra digit line pair capacitance, i.e., between a given digit line and its complement. A prior art architecture that achieves this result is shown in FIG. 2B. This twisting architecture is interesting in that it has no best or worse case. Regardless of the status of the digit lines, a coupling coefficient of C=0.75 will always result. If we take digit line Digitl=`1` as an example, we see that Digit1 is always bordered by Digit1*=`0` on one side. Because this potential difference occurs for the entire length of Digit1, Digit1* contributes C=0.5 to the coupling coefficient of Digit1. On the side of Digit1 that is not adjacent to Digit1*, we see that Digit1 meets with Digit2=`1` for one-fourth of its length (which contributes nothing to the coupling coefficient because there is no potential difference between Digit1 and Digit2), and meets with Digit2*=`0` for one-fourth of its length. Thus, Digit2* contributes another C=0.125 to the coupling coefficient of Digit1 for a total of C=0.625. Likewise, Digit1 meets with Digit0* for one-fourth of its length, which contributes another C=0.125 to the coupling coefficient of Digit1 for a total of C=0.75. If the logic states of Digit2 and Digit2* or Digit0 and Digit0 are changed to `0` and `1` respectively, the nature of the coupling with respect to Digit1 does not change, because Digit1 will still "see" a logic state of `0` on one full side and half of its other side. Hence, using the twisting architecture of FIG. 2B, the coupling coefficient of any digit line is C=0.75. This provides a benefit over the non-twisted architecture of FIG. 2A in that the amount of coupling, and hence the rate at which the digit lines can be accessed, are constant. However, the twisting architecture of FIG. 2B, while providing constant coupling, also tends to slow access to the digit lines down. In effect, the architecture of FIG. 2B averages the coupling, and indirectly the speed, of the digit lines when compared with the non-twisted architecture of FIG. 2A.
Another digit line twisting architecture that is known in the art is shown in FIG. 2C. This architecture has been used on DRAM products manufactured by Micron Technology, Inc., including part number MT48LC16M4 (16M.times.4 synchronous DRAM). As used on these Micron DRAMs, a single twist 24 appears at the center of the subarray 16 that the digit lines 14 are contained in. This architecture has the benefit of reducing that portion of the coupling coefficient that is provided by a given digit line's complement. The architectures of FIGS. 2A and 2B show that any given digit line is always bordered on one full side by its complement. The architecture of FIG. 2C reduces this intra digit line capacitance by physically separating a given digit line and its complement for at least a portion of the digit line's progression through the subarray.
In contrast to the digit lines, a problem that is arising in modern day DRAMs is that the data lines 18 are becoming longer. As can be seen in FIG. 1A, the data bus 21 runs along several subarrays, and is much longer than any of the digit lines 14 appearing within a given subarray 16. Moreover, as designers are forced to pack more structures into limited layout space, the data bus is being built with data lines that are narrower and packed ever closer together. Accordingly, the problems of parasitic capacitance have become a bigger issue with respect to the data bus. Yet, the inventors are not aware of the use of any architectural strategies to reduce parasitic capacitances in a DRAM data line bus. The present invention provides an architecture that achieves this goal, and hence improves the coupling coefficient and speed on DRAM devices.